/*
 *Copyright (c) 2024 Black Sesame Technologies
 *
 *Licensed under the Apache License, Version 2.0 (the "License");
 *you may not use this file except in compliance with the License.
 *You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 *Unless required by applicable law or agreed to in writing, software
 *distributed under the License is distributed on an "AS IS" BASIS,
 *WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *See the License for the specific language governing permissions and
 *limitations under the License.
*/


#ifndef _C1200_REGBASE_H
#define _C1200_REGBASE_H


/***********************************************************/
#define SOC_BASE_SRAM_SECURITY					(0x00100000)	//512k
#define SOC_BASE_SRAM_SAFETY						(0x04C00000)	//1M
#define SOC_BASE_SRAM_REALTIME0					(0x04000000)	//4M
#define SOC_BASE_SRAM_REALTIME1					(0x04400000)	//4M
#define SOC_BASE_SRAM_SWITCH0						(0x04800000)	//2M
#define SOC_BASE_SRAM_SWITCH1						(0x04A00000)	//2M
#define SOC_BASE_SRAM_SOC								(0x05100000)	//512k

//#define SOC_BASE_SRAM0_WAKEUP						(0x00100000)	//512k
//#define SOC_BASE_SRAM1_WAKEUP						(0x00100000)	//512k


/***********************************************************/
//CRM ctrl addr
#define SOC_LSP0_CRM_REGBASE						(0x20000000)//4KByte
#define SOC_LSP1_CRM_REGBASE						(0x20020000)//4KByte
#define SOC_SWLSP_CRM_REGBASE						(0x217a0000)//4KByte
#define SOC_SW_CRM_REGBASE							(0x217b0000)//4KByte
#define SOC_TOP_CRM_REGBASE							(0x30002000)//4KByte

#define SOC_TIMESTAMP_SEC_APB_CSR					(0x30008000)//4KByte
#define SOC_TIMESTAMP_NOSEC_APB_CSR					(0x30009000)//4KByte
#define SOC_TIMESTAMP_GTC_CSR						(0x3000A000)//4KByte

#define SFT_SEC_SAFETY_CRM_REGBASE			(0xc0030000)//4KByte
#define SFT_SAFETY_LSP_CRM_REGBASE			(0xc175f000)//4KByte
#define SFT_RT_LSP0_CRM_REGBASE					(0xd0000000)//4KByte
#define SFT_RT_LSP1_CRM_REGBASE					(0xd0020000)//4KByte
#define SFT_RT_CRM_REGBASE							(0xd0033000)//4KByte

#define SFT_CSR_REGBASE									(0xc0031000)//4KByte
#define RT_CSR_REGBASE									(0xd1036000)//4KByte


/***********************************************************/
#define GMAC_SAFETY_GMAC_EXTERNAL				(0xC0100000)
#define GMAC_SAFETY_GMAC_INTERNAL				(0xC0200000)
#define GMAC_SW_GMAC_INTERNAL						(0x217B8000)
#define GMAC_RT_GMAC_INTERNAL						(0xD1200000)
#define XGMAC_SOC_EXTERNAL							(0x32070000)
#define XGMAC_SOC_INTERNAL							(0x22500000)

/***********************************************************/
//safety system addr
#define SDMA_BASE_ADDR          (0xC0020000)
#define SEC_SAFETY_CRM_ADDR     (0xC0030000)
#define SAFETY_CSR_ADDR         (0xC0031000)
#define SAFETY_PMU_ADDR         (0xC0032000)
#define SAFETY_PMM_ADDR         (0xC0034000)
#define SAFETY_PVT_ADDR         (0xC0035000)
#define STANDBY_PMM_ADDR        (0xC0037000)
#define SAFETY_R5_TCM0_ADDR     (0xC0300000)
#define SAFETY_R5_TCM1_ADDR     (0xC0310000)

#define SAFETY_R5_CORSIGHT_ADDR (0xC0080000)
#define SAFETY_R5_CSR_ADDR      (0xC00Bf000)

#define GIC_BASE_ADDR           (0xC1700000)

///////////////LOW SPEED IO////////////////
#define I2C0_BASE_ADDR	        (0xC1740000)
#define I2C1_BASE_ADDR	        (0xC1741000)
#define SMBUS0_BASE_ADDR        (0xC1742000)
#define SMBUS1_BASE_ADDR        (0xC1743000)
#define UART0_BASE_ADDR         (0xC1744000)
#define UART1_BASE_ADDR         (0xC1745000)

#define SPI0_BASE_ADDR	        (0xC1748000)
#define SPI1_BASE_ADDR	        (0xC1009000)
#define SPI2_BASE_ADDR	        (0xC100A000)
#define PWM0_BASE_ADDR	        (0xC174C000)
#define GPIO0_BASE_ADDR	        (0xC174D000)
#define GPIO1_BASE_ADDR	        (0xC174E000)
#define GPIO2_BASE_ADDR	        (0xC174F000)
#define GPIO3_BASE_ADDR	        (0xC1750000)
#define WDT0_BASE_ADDR	        (0xC1752000)
#define WDT1_BASE_ADDR	        (0xC1753000)
#define CANFD0_BASE_ADDR        (0xC1760000)
#define CANFD1_BASE_ADDR        (0xC1768000)

#define I2C_IP_CNT 2
#define TIMER_PWM_IP_CNT 1


//realtime addr
#define RT_R5_CSR0_ADDR         (0xD167F000)
#define RT_R5_CSR1_ADDR         (0xD16BF000)
#define RT_R5_CSR2_ADDR         (0xD16FF000)
#define RT_CRM_ADDR             (0xD1033000)
#define RT_BIST_ADDR            (0xD1034000)
#define RT_PMM_ADDR             (0xD1035000)
#define RT_R5_TCM0_ADDR         (0xD1300000)
#define RT_R5_TCM1_ADDR         (0xD1310000)
#define RT_R5_TCM2_ADDR         (0xD1400000)
#define RT_R5_TCM3_ADDR         (0xD1410000)
#define RT_R5_TCM4_ADDR         (0xD1500000)
#define RT_R5_TCM5_ADDR         (0xD1510000)

//switch sub system address
#define SWITCH_CRM_ADDR         (0x217B0000)
#define SWITCH_R5_0_CSR         (0x2187F000)
#define SWITCH_R5_1_CSR         (0x218BF000)
#define SWITCH_R5_2_CSR         (0x218FF000)

#define SWITCH_TCM0_ADDR        (0x20100000)
#define SWITCH_TCM1_ADDR        (0x20110000)
#define SWITCH_TCM2_ADDR        (0x20200000)
#define SWITCH_TCM3_ADDR        (0x20210000)
#define SWITCH_TCM4_ADDR        (0x20300000)
#define SWITCH_TCM5_ADDR        (0x20310000)

//switch R5 csr
#define SWITCH_R5_0_CORE0_CONFIG   (SWITCH_R5_0_CSR+0x20)
#define SWITCH_R5_0_CORE0_STATUS   (SWITCH_R5_0_CSR+0x40)
#define SWITCH_R5_0_CORE1_STATUS   (SWITCH_R5_0_CSR+0x48)


/***********************************************************/
enum cpu_platform_type {
	r5_security=0,
	r5_safety,
	r5_realtime,
	r5_switch,
	r5_acluster,
};

enum mii_type {
	MII_TYPE_NULL=0,
	MII_TYPE_GMII,
	MII_TYPE_XGMII,
	MII_TYPE_MAX,
};



#endif //_C1200_REGBASE_H
